Conventionally, the IGBT has been known as a power semiconductor device which can operate at a relatively high speed and which can also deal with a great amount of power. The application of IGBT devices in great-power control apparatus has been increasing in recent years.
FIG. 5 is a cross-sectional view showing one example of the structure of the conventional IGBT.
The IGBT comprises a high-concentration p-type semiconductor (p.sup.+) substrate 51, an n-type semiconductor buffer layer (an n-buffer-layer) 52, a low-concentration n-type semiconductor (n.sup.-)layer 53, p-type semiconductor (p) regions 54, high-concentration n-type semiconductor (n.sup.+) regions 55, high-concentration p-type semiconductor (p.sup.+) regions 56, gate oxide films 57, first silicon oxide films 58, second silicon oxide films 59, a collector electrode 60, an emitter wiring electrode 61, a gate wiring electrode 62, gate electrodes 63, an emitter wire electrode 64 and a gate wire electrode 65. An emitter bonding pad region 66 of the IGBT is constituted of the first silicon oxide film 58, the second silicon oxide film 59 and the emitter wiring electrode 61. A gate bonding pad region 67 is constituted of the first silicon oxide film 58, the second silicon oxide film 59 and the gate wiring electrode 62.
The n-buffer layer 52 and the n.sup.- layer 53 are successively formed over the substrate 51, thus constituting a base body. The p.sup.+ regions 56 are formed on those portions of the base body surface on the n.sup.- layer 53 side which corresponds to the emitter bonding pad region 66 and the gate bonding pad region 67, and also, the p regions 54 are formed on the other portions of the base body surface. The collector electrode 60 is formed on the base body surface on the p.sup.+ substrate 51 side. One or more n.sup.+ regions 55 are formed inside of each of the p 54. The first silicon oxide films 58 are formed on the surfaces of the p.sup.+ regions 56, and then, the second silicon Oxide films 59 are formed on the first silicon oxide films 58, thereby forming the emitter bonding pad region 66 and the gate bonding pad region 67. The gate oxide film 57 is formed between adjacent two of the n.sup.- regions 55 so as to extend over the regions 54 and the n.sup.- layer 53, and the gate oxide film 57 is also formed partially on the surfaces of the p.sup.+ regions 56. The gate electrodes 63 are disposed on these gate oxide films 57, and then, the second silicon oxide films 59 are formed on these gate electrodes 63. The emitter wiring electrode 61 is formed on the second silicon oxide films 59 except the gate bonding pad region 67, and the emitter wiring electrode 61 is electrically connected to the n.sup.+ regions 55 and the regions 54 through those portions where the second silicon oxide film 59 is not provided. The gate wiring electrode 62 is formed on the second silicon oxide film 59 in the gate bonding pad region 67, and the gate wiring electrode 62 is electrically connected to the gate electrodes 63 through that portions where the second silicon oxide film 59 is not provided. The emitter wire electrode 64 made of aluminum, gold or the like is bonded on the surface of the emitter wiring electrode 61 by ultrasonic bonding, and also, the gate wire electrode 65 made of aluminum, gold or the like is bonded on the surface of the gate wiring electrode 62 by ultrasonic bonding.
In this case, the first and second silicon oxide films 58 and 59 are interposed between the emitter wiring electrode 61 and the p.sup.+ region 56 and between the gate wiring electrode 62 and the p.sup.+ region 56, so that pressures exerted on the p.sup.+ regions 56 are lessened when the emitter wire electrode 64 is bonded on the emitter wiring electrode 61 and when the gate wire electrode 65 is bonded on the gate wiring electrode 62, thereby preventing silicon crystal in the p.sup.+ regions 56 from being broken by the above-mentioned pressures.
The IGBT with the above-described structure operates in the following manner.
A low (-) potential is applied to the emitter wiring electrode 61 through the emitter wire electrode 64, a high (+) potential is applied to the collector electrode 60, and a high (+) potential is applied to the gate wiring electrode 62 through the gate wire electrode 65. An n inversion layer is formed on the surface of the p region 54 in the vicinity of the gate oxide film 57 under the gate wiring electrode 62, and an electron current flows to the p.sup.+ substrate 51 via the layer 55, the above-mentioned n inversion layer, the n.sup.- layer 53 and the n buffer layer 52. This electron current promotes injection of hole current from the p.sup.+ substrate 51, and consequently, conductivity of the n buffer layer 52 and the n.sup.- layer 53 are modulated to thereby generate an electric current flowing from the collector electrode 60 to the emitter wiring electrode 61. At this time, modulation of the conductivity of the n.sup.- layer 53 causes a resistance in the IGBT to be about one hundredth lower so that a large current can be conducted in the IGBT.
Such an IGBT can conduct a current larger than other power transistors. For example, when comparisons are performed with elements of voltage capacity 600 V, the current capacity of the IGBT is about twice larger than that of a bipolar transistor and about four times larger than that of a power MOSFET. As a result, for example, while a chip of 7 mm square is required for constituting a bipolar transistor of current capacity 25 A, an IGBT of the same current capacity 25 A can be constituted by a smaller chip of about 5 mm square.
By the way, since a bipolar transistor and an IGBT having the same current capacity require emitter wire electrodes having the same diameter and emitter bonding pad regions having the same area, this type of IGBT involves a structural problem that it has a higher ratio of an area occupied by the bonding pad region on the chip than the bipolar transistor.
FIG. 6 is a cross-sectional view showing one example of the structure of a conventional IGBT intended to solve this structural problem. In FIG. 6, the same component parts as shown in FIG. 5 are denoted by common reference numerals.
The example of IGBT shown in FIG. 5 (hereinafter referred to as the first example) and the example of IGBT shown in FIG. 6 (hereinafter referred to as the second example) have a mere difference in that the emitter bonding pad region 66, to which the emitter wire electrode 64 is bonded, is provided in the IGBT in the first example whereas, in the second example, the emitter wire electrode 64 is directly bonded to the emitter wiring electrode 61 formed on the gate electrode 63 so that the IGBT does not include the emitter bonding pad region 66. Except for this difference, the first example and the second example are structurally the same.
According to the second example, the region in which an emitter current directly flows (the current conduction region) also functions as the wire bonding region for the emitter wire electrode 64. Consequently, when the second example is compared with the first example having substantially the same size, a ratio of occupation of the current conduction region in the IGBT can be made much higher than that of the first example, and also, processing of a great current can be dealed with.
Especially recently, in the field of IGBT, the chip size has been enlarged, and parallel connection of chips has been developed. As a result, IGBT devices which can deal with a great current of about several hundred ampere (A) are available in the market. In the case where an IGBT of such a structure is arranged to have the structure of the first example, the emitter bonding pad regions 66 must be formed at several tens of positions so that the emitter bonding pad regions 66 will occupy an extremely large area. However, the second example is highly advantageous in that it does not require such an occupied area.
In each of the conventional IGBT devices described above, a current is relatively small, and therefore, wire electrodes having a small diameter are employed. For example, the emitter wire electrode 64 made of aluminum having a diameter of 300 microns (.mu.m) is bonded to the emitter bonding pad region 66. In this case, silicon crystal in the p.sup.+ region 56 are hardly damaged by the pressure at the time of the bonding operation.
However, in order to increase a current to be dealed by the IGBT, the diameter of the emitter wire electrode 64 must be enlarged. When the emitter wire electrode 64 having the enlarged diameter is bonded to the emitter bonding pad region 66, silicon crystal in the p.sup.+ region 56 are damaged by a large pressure generated at the time of the bonding operation, thereby deteriorating the blocking voltage of the IGBT. Similarly, when the gate wire electrode 65 is bonded to the gate bonding pad region 67, substantially the same phenomenon induces deterioration of the blocking voltage. In this case, the rate of occurrence of the blocking voltage deterioration increases as the diameter of the emitter wire electrode 64 and the gate wire electrode 65 is enlarged in accordance with an increase in the current to be dealed by the IGBT. For example, when the diameter of the emitter wire electrode 64 and the gate wire electrode 65 is about 500 microns (.mu.m), deterioration in the blocking voltage of the IGBT is exhibited quite remarkably.
The present invention has been proposed to solve the problem of deterioration in the blocking voltage.